All screenshots included in this manual are taken from SpyGlass as an iShell .. plugins may provide actions, if the user clicks on an object on the screen, e.g. Atrenta spyglass user guide pdf. Both the printer driver and application software are compressed. CMOS Memory Clearing Header JP1 This header. Using Atrenta Spyglass in GUI mode: For all the documentation of the spyglass, do “spydocviewer &” in the command promptof the unix machine.

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Power figures for hierarchical modules There is a feature of Spyglass Power which gives atrenra atrenta spyglass user guide graph of every activity in atrenta spyglass user guide design, allowing us to see the activity is for a particular block, even without actually doing any spyglasw computations.

Our architects use Spyglass at the architectural level as follows: We wrote a C program to compile these individual power estimates, taking in account their duration, to create a power scorecard for the CPU.

We can extract a lot of different reports with Spyglass, such as what is clocked and what is not clocked; this helps to guide us in developing micro-architecture. Sign up for the DeepChip newsletter.

Spyglass Power for both architectural and RTL power reduction

At my company we have 2 primary types of Spyglass users: The register file was our greediest module. Spyglass has no problems with mixed language support. We use it, it works.


The architect then runs Spyglass Power to find power bugs. Email in your dissenting letter and it’ll be published, too.

Suffice to say, that is absolutely precise enough to make design decisions for atrenta spyglass user guide reduction. The other primary users of Spyglass power are our experts in low-power design. He then did final analysis for clock-gating.

First we run simulation vectors to functionally verify our design; we mostly design in VHDL, with some Verilog. We are looking at new design optimization techniques using the substrate, based atrenta spyglass user guide substrate polarization that changes, for example, the transistor power consumption and speed. Spyglass Power looked at every single register and arrenta inside the block — there can be 10,’s of them — to see if it could gate them.

Read what EDA tool users really think. Anything said here is just one engineer’s opinion. We work on advanced design technologies with industrial partners such as ST Microelectronics. The memory power reduction comes from rules such as: We are happy with Spyglass. This is a discussion. I atrenta spyglass user guide estimate we’ve had a 2 months savings with it.

We input simulation vectors to Spyglass, to get power estimates. So far, artenta haven’t seen any serious problems.

The tool is stable atrenta spyglass user guide we get same-day support. Next, we run Spyglass Power, using the simulation vectors. Spyglass’ sequential analysis and equivalence checking atrenta spyglass user guide us test strenta.

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Typically, this second stage includes optimizations focused on applying specific sequential and formal techniques to reduce register and memory power. Spyglass’ design flow integration allows our designers to focus on the results of the tool: We have recently used Spyglass on two different chips; below I have 4 sample case studies of our power reduction results.

This opportunity to consider programmable architectures in terms of power consumption especially makes sense for compiler and hardware designers looking for power saving. For every instruction and couple of instructions, we generated different simulation vectors.

These are highly skilled designers who usually assume that a tool cannot do better than they can! Our typical projects tend to atrenta spyglass user guide months.

We intend, in the coming weeks, to use Spyglass Power for defining using its power estimation feature atrenta spyglass user guide right set of operating points voltage, frequency for our Dynamic Voltage and Frequency Scaling.

The architect removed these power bugs by manually adding clock- gating cells at the cluster-level. This was useful gguide power planning at SoC level during early design development phase SoC power architecture specification.